Memory devices, such as static random access memory (“SRAM”) devices and dynamic random access memory (“DRAM”) devices are in common use in a wide variety of electronic systems, such as personal computers. Memory devices include one or more arrays of memory cells, which in DRAM devices, are small capacitors that are arranged in rows and columns. Data is represented by the presence or absence of a charge on the capacitor in the memory cell. Data can be stored in the memory cells during a write operation or retrieved from the memory cells during a read operation. If the capacitor in the addressed or selected memory cell is charged, then the capacitor discharges onto a digit line associated with the memory cell, which causes a change in the voltage on the digit line. On the other hand, if the capacitor in the selected memory cell is not charged, then the voltage on the digit line associated with the memory cell remains constant. The change in voltage (or lack of change) on the digit line can be detected to determine the state of the capacitor in the selected memory cell, which indicates the value of the data bit stored in the memory cell.
Sense amplifiers are used to improve the accuracy of determining the state of the capacitor in selected memory cells. As known in the art, when the memory cell array is accessed, a row of memory cells are activated, and the sense amplifiers amplify data for the respective column of memory cells by coupling each of the digit lines of the selected column to voltage supplies such that the digit lines have complementary logic levels. A conventional sense amplifier 100 of a DRAM memory array is shown in FIG. 1. The sense amplifier 100 is coupled to a pair of complementary digit lines DIGIT and DIGIT_ to which a large number of memory cells (not shown) are connected. The sense amplifier 100 includes a pair of cross-coupled PMOS transistors 102, 104. The sources of the PMOS transistors 102, 104 share a common node to which a PMOS activation signal ACT is coupled during operation. The ACT signal is typically provided by a power supply voltage (not shown) during operation. The sense amplifier 100 also includes a pair of cross-coupled NMOS transistors 112, 114. The drains of the NMOS transistors 112, 114 also share a common node to which an NMOS activation signal RNL_ is coupled during operation. The RNL_ signal is typically provided by being connected to ground (not shown) during operation. The sense amplifier 100 is configured as a pair of cross-coupled inverters in which the ACT and RNL_ signals provide power and ground, respectively. The digit lines DIGIT and DIGIT_ are additionally coupled together by an equilibration transistor 110 having a gate coupled to receive a control signal EQ.
In operation, the sense amplifier 100 equilibrates the digit lines DIGIT and DIGIT_, senses a differential voltage that develops between the digit lines DIGIT and DIGIT_, and then drives the digit lines to corresponding logic levels. In response to an active HIGH EQ signal the equilibration transistor 110 turns ON, connecting the digit lines DIGIT and DIGIT_ to each other and equilibrating the digit lines to the same voltage. The digit lines are typically equilibrated to VCC/2, which keeps the PMOS transistors 102, 104 and the NMOS transistors 112, 114 turned OFF. After the differential voltage between the digit lines DIGIT and DIGIT_ has reached substantially zero volts, the EQ signal transitions LOW to turn OFF the transistor 110.
When a memory cell is accessed, the voltage of one of the digit lines DIGIT or DIGIT_ increases slightly, resulting in a voltage differential between the digit lines. While one digit line contains a charge from the accessed cell, the other digit line does not and serves as a reference for the sensing operation. Assuming, for example, the voltage on the DIGIT line increases, the voltage level of the DIGIT line increases slightly above VCC/2 causing the gate-to-source voltage of the NMOS transistor 114 to be greater than the NMOS transistor 112. The RNL signal is activated, driving the common node of the NMOS transistors 112, 114 to ground, switching the NMOS transistor 114 ON. As a result, the complementary digit line DIGIT_ is coupled to the active RNL_ signal and is pulled to ground. In response to the low voltage level of the DIGIT_ line, the gate-to-source voltage of the PMOS transistor 102 increases, and in response to activation of the ACT signal, is turned ON due to the gate-to-source voltage being larger than the PMOS transistor 104. The DIGIT line is consequently coupled to the power supply voltage as provided by the active ACT signal, and the PMOS transistor 102 drives the digit line DIGIT towards the power supply voltage. Thereafter, the voltage on the digit line DIGIT further increases and the voltage on the complementary digit line DIGIT_ further decreases. At the end of the sensing period, the NMOS transistor 114 has driven complementary digit line DIGIT_ to ground by the active RNL_ signal and the PMOS transistor 102 has driven the digit line DIGIT to the power supply voltage VCC by the active ACT signal.
Random threshold voltage mismatch of transistor components in conventional sense amplifiers 100 are undesirable because deviations of the threshold voltage may abruptly cause an imbalance in the sense amplifier that can erroneously amplify input signals in the wrong direction. For example, the offset due to a threshold voltage mismatch of the sense amplifier 100 may be amplified by the large gain of the NMOS transistors 112, 114, as will be understood by one skilled in the art. Consequently, the sense amplifier 100 would likely amplify the signal on the asserted digit line incorrectly, resulting in reading the incorrect data. Errors and delays due to mismatched threshold voltages in sense amplifiers ultimately affect the overall accuracy of memory operations. While efforts have been made to compensate for threshold voltage offsets, such compensation methods typically increase memory access time, occupy chip space and increase power consumption.
Therefore, there is a need for a sense amplifier designed to have tolerance to voltage threshold mismatch of transistor components included in the sense amplifier.